hardware

douglasawh's picture

Hardware Hacking with Beagle Boards

"The Beagle Board is a low-power, low-cost Single-board computer produced by Texas Instruments in association with Digi-Key, designed with open source development in mind, to demonstrate the Texas Instrument's OMAP3530 system-on-a-chip. The board was developed by a small team of TI engineers." - http://en.wikipedia.org/wiki/Beagle_Board
Date
December 5, 2009 - 2:00pm - 4:00pm

Location

Ashman Branch (Madison Public Library)
733 N High Point Rd
Madison, WI 53717
abraham's picture

SCARAB: A Single Cycle Adaptive Routing and Bufferless Network / Light Speed Arbitration and Flow Control for Nanophotonic Interconnects

Mitch Hayenga: "SCARAB: A Single Cycle Adaptive Routing and Bufferless Network"

Recent research has proposed bufferless routers as a means to alleviate the power and area constraints for on-chip networks. To date all designs exhibit poor operational frequency, throughput, or latency. In this paper, we propose an efficient bufferless router which lowers average packet latency by 17.6% and dynamic energy by 18.3% over existing bufferless on-chip network designs.

--------------------------------

Dana Vantrease: "Light Speed Arbitration and Flow Control for Nanophotonic Interconnects"
Date
November 24, 2009 - 4:00pm

Location

UW Madison Computer Science
1210 W. Dayton St. Room 1221
Madison, WI 53703
abraham's picture

Location, Location, Location: Choosing Wisely in the Ever-expanding Area of Silicon Real Estate

In the near term, Moore's law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents the integration of a large number of memory controllers on-chip. With many cores, and few memory controllers, where to locate the memory controllers in the on-chip interconnection fabric becomes an important and as yet unexplored question. In this paper we show how the location of the memory controllers can reduce contention (hotspots) in the on-chip fabric and lower the variance in reference latency. This in turn provides predictable performance for memory-intensive applications regardless of the processing core on which a thread is scheduled. We explore the design space of on-chip fabrics to find optimal memory controller placement relative to different topologies (i.e., mesh and torus), routing algorithms, and workloads. 

 Bio: 
Date
October 13, 2009 - 3:30pm

Location

UW Madison Computer Sciences
1210 W Dayton St. Room 1221
Madison, WI 53703
abraham's picture

Energy-Efficient Software and Hardware for Data Centers

  Companies such as Amazon, Google, Microsoft, and Yahoo are building  several
  large  data  centers containing tens of thousands of machines to provide the
  computational capability to support  a  variety  of  web  services  such  as
  search,  email,  and online shopping. Energy costs for operating and cooling
Date
July 22, 2009 - 11:00am - 1:00pm

Location

UW Computer Science Building
1210 W. Dayton St Room 3310
Madison, WI 53703
abraham's picture

Symmetric and Asymmetric Chip Multi-Core: Applications, processors and scheduling - Initial Thoughts

Computational requirement is characterized by a wide range of diverse appli-
  cations. This wide range of applications is  applicable  to  all   computing
  markets  (e.g. Mobile, Desktop and Server). In many cases these applications
  coexist and run simultaneously on a specific system. The applications differ
  from  each  other  by  their  practical  requirements  e.g. performance, BW,
  latency, power limitation, performance/power requirement, QoS,  differential
  services  etc.  Essentially, these requirements are asymmetric/Heterogeneous
  and calls for reciprocal HW/OS implementation to enable a better response to
  the applications' need.

  On  the  other hand, device's power limitation will drive for Asymmetric HW.
Date
June 18, 2009 - 11:00am

Location

UW Computer Science building
1210 W. Dayton St Room 3310
Madison, WI 53706